1. Field of the Invention
The present invention relates to semiconductor processing, and more specifically to a method of reflowing copper to form interconnections in a semiconductor device.
2. Background Information
As the demand for cheaper, faster, lower power microprocessors increases, so must the device packing density of the integrated circuit. Very large scale integration (VLSI) techniques have continuously evolved to meet the increasing demand. All aspects of the integrated circuit must be scaled down to fully minimize the device dimensions of the integrated circuit. In addition to minimizing the device themselves, the dimensions of the electrical interconnections which integrate those devices must also be minimized.
Interconnections increasingly determine the limits in performance, reliability, and power consumption for semiconductor devices. As VLSI dimensions reach into the deep-submicron Ultra Large Scale Integration (ULSI) regime, interconnections for such devices require new materials and new processes for fabrication.
Currently, aluminum (Al) and aluminum alloys are the most commonly used conductive materials for electrical interconnections. Aluminum and its alloys have been fully characterized for use as electrical interconnections and technology has been developed to aid in the formation of aluminum interconnections. While aluminum has very attractive features for use as an electrical interconnection, such as low electrical resistivity and strong adhesion to silicon dioxide (SiO.sub.2), as the dimensions of semiconductor devices and their interconnections decrease, the deficiencies of aluminum and its alloys become limiting factors in achieving superior performance. For example, as electrical interconnections become deeper and narrower, it becomes harder to fabricate such interconnections using aluminum without the formation of voids. Void formation is described in detail below with respect to copper, however, it will be obvious to one with ordinary skill in the art that void formation in aluminum interconnections occurs in a similar manner to that of void formation in copper interconnections. Additionally, with decreasing dimensions, design rules become increasingly restricted by aluminum interconnection reliability concerns such as electromigration, stress-induced void formation, hillock suppression, and current density limitations.
For these reasons, the microelectronics industry has recently migrated towards the investigation of more robust, more conductive metals for use in interconnection technology such as Copper (Cu). Copper is approximately 40% lower in resistivity than aluminum and is much more resistant to reliability problems such as electromigration. One of the main reasons why the use of copper and its alloys for interconnection applications has not been more widespread is because a manufacturable dry-etch process has not yet been demonstrated that can pattern copper-based materials using standard photolithographic techniques. FIGS. 1a-1d illustrate a dry-etch process used to try to pattern copper and copper alloy interconnects.
In FIG. 1a, a metal layer 110 has been deposited above silicon dioxide (SiO.sub.2) layer 100. For this example, metal layer 110 may be made of copper or a copper alloy. A photoresist layer 120 has been deposited and patterned on top of metal layer 110. Processes for photoresist deposition and patterning are well known in the art and are therefore not described herein.
The structure of FIG. 1a is then subjected to a dry-etch process, for example, reactive-ion etch (RIE), in order to etch away the exposed portions of metal layer 110. The unexposed portions of metal layer 110 which remain after the etch is performed form interconnects 130. As illustrated in FIG. 1c the photoresist is then removed. Finally, oxide 140 is deposited between the interconnections 130, as is illustrated in FIG. 1d.
The problem with dry-etch processes for forming copper interconnects is that all the copper halides have low vapor pressures at room temperature. Etching at low vapor pressures equates to slower etch rates and longer processing times. High vapor pressures allow materials to etch faster, however copper halides, such as chloride and fluoride, only have high enough vapor pressures for etching at temperatures above 200.degree. C. which is too high for most photoresists. To implement the use of copper as a microelectronic interconnection material, it has therefore become necessary to develop alternate patterning techniques.
One technique is known as damascene. In damascene, a dielectric layer is deposited onto a substrate, patterned, and etched back such that the trenches, grooves, vias, or other recessed regions etched into the dielectric layer represent the desired metal interconnection pattern. A conductive material is then deposited over the entire surface of the device, filling in the recessed regions and blanketing the surface of the dielectric layer. Next, the conductive material is etched back to a degree such that the conductive material becomes electrically isolated within the recessed regions etched out of the dielectric layer.
One problem with the damascene process, however is that it is difficult to fill the trench or via with a conductive material without the formation of voids or tunnels which result in interconnections that would have significant reliability problems and degraded electrical performance. Such void formation would ultimately degrade semiconductor device yields thereby adding to the total manufacturing cost. FIGS. 2a-2e illustrate a damascene process.
FIG. 2a illustrates a semiconductor substrate 200 with a dielectric layer 240 deposited on its surface. Dielectric layer 240 is then etched using conventional etch techniques to create trenches 250, as illustrated in FIG. 2b. FIG. 2c illustrates the semiconductor substrate of FIG. 2b during the sputter deposition of a conductive or metal layer 230 on its surface. Note that gap 260 has formed in the metal layer 230.
As the conductive material is deposited onto the substrate in FIG. 2c, the conductive material may be deposited at a faster rate on the top surface and along the walls nearer the top surface than at the bottom of trench 250, thus forming gap 260 and overhangs 270. During deposition, overhangs 270 become larger making it increasingly more difficult to deposit and flow any more conductive material into gap 260. Eventually, as illustrated in FIG. 2d, overhangs 270 will touch and "pinch" the opening of trench 250 shut. Thus, the flow of the conductive material into gap 260 is stopped altogether and void 280 is formed. If the top surface of the substrate is etched back at this point, as illustrated in FIG. 2e, void 280 will remain inside trench 250 leading to the problems described below as well as limiting the current carrying capability of the electrical interconnection.
Voids can cause significant problems in a semiconductor manufacturing process and are considerable issues for sputtered and evaporated films. One problem with voids is that they can trap impurities which can harm the semiconductor device in subsequent process steps. Assuming metal layer 230 of FIG. 2d was etched back using some sort of chemical etching process, the etchant chemicals may become trapped within the void 280 and cause additional etching or corrosion of electrical interconnection 230 even after the etchant has been removed from the surface of the substrate. These trapped etchant chemicals may then contaminate the semiconductor device and could degrade reliability.
Trapped etchant chemicals may also continue to etch the electrical interconnection 230 resulting in the thinning of electrical interconnection 230 and cause the creation of a electrical open, thereby resulting in a failure. Interconnection thinning may also lead to other reliability problems such as electromigration and current-carrying limitations. Another problem is that trapped contaminants may expand if the semiconductor substrate is subjected to subsequent high temperature processing steps. Such expansion could cause significant damage to adjoining surface features of the semiconductor device. Additionally, trapped contaminants may escape during, for example, a subsequent process step thereby contaminating all other semiconductor devices within the process chamber.
It should be noted and it will be obvious to one with ordinary skill in the art, that the potential for forming voids is greatly increased by attempting to fill grooves of significantly varying widths together on a single substrate at the same interconnection level. This is because these deposition processes are typically optimized to fill a groove (or trench) of a particular width and depth. While such optimization techniques may be suitably employed to fill interconnections of one particular width on a semiconductor substrate, the problem is that grooves of other widths for which the process has not been optimized run a much higher risk of void formation. This makes interconnection technology dependent on individual device layout. Such dependence degrades the manufacturability of such processes.
Thus, what is needed is a method for reflowing conductive layers into vias (or trenches) that decreases the formation of voids, decreases fabrication time, and increases the reliability of the electrical interconnections of a semiconductor device.